1. Field of the Invention
The present invention relates to an electric fuse for a redundancy circuit used as a redundancy circuit in a semiconductor memory and, more particularly, to a structure of an electric fuse for a redundancy circuit capable of being blown out easily and reliably at a low voltage.
2. Description of the Prior Art
As the capacity of a MOS dynamic RAM becomes larger, it is inevitable that the size of a chip increases and a manufacturing process becomes fine. Because of this increase of the size of a chip and a fine process, the rate of existence of crystal defects in one chip increases, and a larger influence comes to be exerted on an occurrence of defective memory cells by pattern defects and dust produced during a manufacturing process. Thus, recently measures have been taken to provide spare redundancy memory cells in a memory chip of a MOS dynamic RAM for replacing defective memory cells produced by a crystal defect, a pattern defect and dust with redundancy memory cells to remedy a memory chip, that is, to use a so-called redundancy circuit.
In a redundancy circuit, fuses for a redundancy circuit are necessary to replace defective memory cells with redundancy memory cells and there are two kinds of fuses, that is, (1) the one which is blown out by a laser light beam, and (2) the one which is blown out by electricity (electric fuse for a redundancy circuit).
FIG. 1 is a block diagram showing a conventional MOS dynamic RAM, comprising a circuit portion for replacing defective memory cells with redundancy memory cells by using a redundancy circuit. Referring to FIG. 1, reference characters Ext. A.sub.O -A.sub.N denote external address signals, a reference numeral 101 denotes an address buffer, reference characters A.sub.O -A.sub.N and A.sub.O -A.sub.N denote output signals and its inverted signals of an address buffer, reference numeral 102 denotes a row decoder, reference numeral 103 denotes a column decoder, reference numeral 104 denotes a sense amplifier, reference numeral 105 denotes a m.times.n memory cell array, reference numeral 106 denotes a fuse control circuit serving as a redundancy circuit using fuses, and reference numeral 107 denotes an address coincidence circuit. In FIG. 1, the column decoder 103 comprises one spare 103S, the sense amplifier 104 comprises one spare 104S and the memory cell array comprises a plurality (m) of spares 105S in the direction of a column. Prior to a description of the drawing, an example and an operation of the fused control circuit 106 are now described.
FIG. 2 is an example of a circuit diagram showing in detail the fuse control circuit 106 serving as a redundancy circuit shown in a block diagram in FIG. 1, in which only a circuit related to the external address signal Ext. A.sub.O is shown for simplification. Referring to FIG. 2, reference characters Q1, Q2, Q3, Q4 and Q6 denote N-channel MOS transistors, reference characters Q5 and Q7 denote P-channel MOS transistors, reference character INV denotes an inverter, reference character R denotes a resistor, reference characters V.sub.PP and V.sub.P2 denote applied voltages, references character T.sub.i denotes an input inputting the external address signal Ext. A.sub.O, reference character T.sub.o denotes an output, reference characters N1, N2 and N3 denote nodes, reference characters A.sub.O and A.sub.O denote output signals from an address buffer, reference numeral 30 denotes a fuse portion and reference characters 4a and 4b denote aluminum lines connected to a fuse portion.
Next, an operation is described. To blow out the fuse portion 30, a voltage of 10-15 V is applied to the input T.sub.i, a voltage of 10-15 V is applied to the V.sub.pp and a voltage higher than 10 V is applied to the V.sub.p2. As a result, the node N1 is rendered to be a value exceeding 10 V and the fuse portion 30 is blown out.
An operation of that circuit when the fuse portion 30 is blown out is described in the following. That is, since the node N2 becomes low level and the node N3 becomes high level, the N-channel MOS transistor Q4 and the P-channel MOS transistor Q5 turn on, while the N-channel MOS transistor Q6 and P-channel MOS transistor Q7 turn off. Therefore, the output A.sub.O of the address buffer is outputted to the output T.sub.o.
Meanwhile, an operation of the circuit when the fuse portion 30 is not blown out is described in the following. Since the node N2 becomes high level and the node N3 becomes low level, the N-channel MOS transistor Q4 and the P-channel MOS transistor Q5 turn off, while the N-channel MOS transistor Q6 and P-channel MOS transistor Q7 become on. Therefore, the output A.sub.O of the address buffer is outputted to the output T.sub.o.
Therefore, the fuse control circuit shown in FIG. 1 has the role of programming the external address signal Ext. A.sub.O depending on whether the fuse portion 30 is blown out or not.
The fuse control circuit 106 shown in FIG. 1 has the above-mentioned function and is connected to the address coincidence circuit 107. If defective cells exist in the memory cell array 105, and a column address in which the defective cells exist and a column address programmed by the fuse control circuit 106 coincide, a portion of an applicable column address of the column decoder 103 is made ineffective and at the same time the spare column decoder 103S is made effective. In that operation, defective cells in the memory cell array 105 can be replaced with the spare memory cell 105S.
FIG. 3A is a plan view showing a structure of an electric fuse for a redundancy circuit used for a redundancy circuit in a conventional MOS dynamic RAM, and FIG. 3B is a sectional view taken along the line 3B--3B in FIG. 3A.
Referring to FIGS. 3A and 3B, a field oxide film 2 is formed on a silicon substrate 1, and is usually of 0.5-1.0 .mu.m in thickness. A fuse portion 30 made of a polycrystal silicon film is formed on the field oxide film 2, and comprises a blowout portion 30c of the width W and terminal portions 30a and 30b connected to the opposite ends of the portion 30c. An insulating film 52 also covers the fuse portion 30, the aluminum line 4 and the field oxide film 2 for insulating protection. The blowout portion 30c is blown out electrically by conducting a current larger than a predetermined current. The terminal portion 30a is connected electrically to an aluminum line 4a by contacts 5a and the terminal portion 30b is connected electrically to an aluminum line 4b by contacts 5b.
FIG. 4 is a view showing only a circuit portion for blowing out an electric fuse for a redundancy circuit out of the fuse control circuit shown in FIG. 2.
Referring to FIG. 4, one end of the fuse portion 30 is connected to a power supply V.sub.pp for current supply via the aluminum line and the other end is connected to the drain of a MOS transistor Q2. The MOS transistor Q2 having its source connected to ground level (OV) and its gate electrode receiving a control clock signal .phi.. In order to blow out the blowout portion of the fuse portion 30, the level of the power supply V.sub.pp is raised up to approximately 10-15 V and also the level of the control clock signal .phi. is raised up to approximately 10-15 V to turn on the MOS transistor. As a result, a current flows from the power supply V.sub.pp through the fuse portion 30 to blow out the blowout portion electrically. At that time, it is important to increase a current density which flows through the blowout portion 30c and it is necessary to make the width W of the blowout portion 30c as small as possible.
Meanwhile, in a conventional electric fuse for a redundancy circuit, the width W of the blowout portion 30c is defined by photolithographic technique, that is, the width W is usually approximately 1 .mu.m. Thus, in order to increase a current density flowing through the blowout portion 30c, it is necessary to increase the level of the power supply V.sub.pp applied and the level of the control clock signal .phi., which become above 10 V in most cases. However, problems were caused that an unfavorable influence could be exerted upon the reliability of a memory chip by application of an overvoltage as high as over 10 V, and in addition, an overvoltage more than 10 V cannot be applied in effect because of a decreased withstand voltage of the pn junction and a decreased withstand voltage between the source and drain of a MOS transistor due to the fact that the manufacturing process becomes fine.
As another prior art, an architecture of a dynamic RAM with redundancy is disclosed and also a redundancy circuit using an electric fuse is described in the United States Pat. No. 4,389,715, entitled "REDUNDANCY SCHEME FOR A DYNAMIC RAM", issued on Jun. 21, 1983 to Eaton, Jr. et al.
As other prior art, a program-type circuit using an electric fuse is described in the paper, entitled "A 256K RAM Fabricated with Molybdenum-Polysilicon Technology" in a digest of technical paper of IEEE International Solid-State Circuits Conference held on Feb. 15, 1980.
As still other prior art, a program-type circuit using an electric fuse and a structure of an electric fuse are described in "Electronics" on pages 121-123 and 127-130, issued by McGraw-Hill Book Company on July 28, 1981.